Design of Low Voltage Quasi-floating Self Cascode Current Mirror

In this paper, a modified structure of self-cascode structure is proposed. In the proposed structure, the MOSFET working in saturation mode is replaced by a Quasifloating gate MOSFET by which the threshold voltage can be scaled, resulting in an increase in the drain-to-source voltage of other MOSFET operating in the linear region. The increased drain-to-source voltage results in a change in the operating region, which here is from linear to saturation regime. To exploit the performance of the proposed structure, the design of the current mirror circuit is shown in this paper. The proposed architecture when compared with its conventional design showed improvement in performance without affecting the other parameters. The complete design is done using MOSFET models of 180nm technology using Spice at supply dual supply of 0.5V. Author


Introduction
The nanometer device dimensions and sub-volt operations have favored the design of high performance digital logic functions. But these devices do not provide satisfactory performance in the case of designing analog circuits which is mainly due to channel l ength modulation (CLM) effect. Among various approaches, the self cascode (SC) MOSFET is widely adopted to reduce the CLM effect (Galup-Montoro, Schneider, and Loss 1994;Gerosa and Neviani 2003). However, the SC structure has a disadvantage of having requirement of large device dimensions. Many solutions have been introduced to compensate such requirements such as Asymmetric threshold voltage (Vth) based SC structure (Fujimori and Sugimoto 1998) dualwork function-gate (DWFG) MOSFET & Zero threshold (ZVT) MOSFET (Na, Baek, and Kim 2012), forward body-biasing technique (Baek, Na, and Kim 2016), etc. However, in such an approach there is a requirement of additional or complicated fabrication processing steps (Baek et al. 2013). The threshold voltage has been continuously an obstacle in circuit design, especially for low voltage analog circuits. The reason behind this is due to the fact that the scaling technique is not applicable on the threshold voltage. In this regard, the minimum supply voltage cannot be scaled below the threshold voltage of MOSFET. Few widely adopted low voltage (LV) low power (LP) techniques that have proved its potential are level shifter technique (Rajput and Jamuar 2001), Bulk Driven technique (Blalock, Allen, and Rincon-Mora 1998), Floating Gate (FG) structure (Hasler and Lande 2001), Quasi-floating Gate (QFG) structure (Ramirez-Angulo et al. 2003;Ramirez-Angulo et al. 2004), and Bulk driven floating/quasi-floating Gate (BDFG/BDQFG) structure (Khateb 2014(Khateb , 2015. These LV LP techniques are categorized as nonconventional techniques. However, the associated drawback of using these techniques is in terms of low transconductance & thus low bandwidth circuits compared to gate driven (GD) MOSFET based designs. Among the aforementioned techniques, FG and its modified design QFG has proven its potential in LV analog design by providing multi-input capacitive connection which favored scaling of the threshold voltage. Apart from this, when QFG combined with BD technique resulting in structure popularly known as BDQFG MOSFET showed improved frequency parameters over of simple BD based designs. Generally, BD based designs offer very low voltage operation but do suffer from poor linearity & extremely low transconductance. So, depending upon the desired performance parameter enhancement of designs, the technique choices are made. For example-few widely cited current mirror circuits reported in the literature based on aforementioned non-conventional techniques can be found as: based on BD (Zhang and El-Masry 2004;Aggarwal, Gupta, and Gupta 2013;Raj et al. 2016a), based on FG (Sharma et al. 2006;Manhas et al. 2008), based on QFG (Lopez-Martin et al. 2008;Esparza-Alfaro et al. 2012;Esparza-Alfaro et al. 2014;Raj et al. 2014a), and based on BDQFG (Raj et al. 2014b(Raj et al. , 2016b(Raj et al. , 2016c(Raj et al. , 2017Bchir, Aloui, and Hassen 2020). In this paper, a modified structure of gate driven Self Cascode (SC) is proposed which uses the Quasi floating gate (QFG) MOSFET. The proposed QFG-SC structure results in the operation of both the MOSFETs in saturation mode. This results in improved performance over conventional gate driven SC structure. Further to evaluate the performance of the proposed QFG-SC, the current mirror design is presented and compared with its conventional architecture. The paper is divided in five sections. Section 2 details on the proposed QFG-SC structure followed for the design of the basic current mirror circuit based on the proposed QFG-SC and as well based on conventional SC structure in section 3. The current mirror designs are supported by their small-signal analysis. The simulation results are discussed in section 4 followed by the conclusion in section 5.

Proposed QFG Self Cascode
A modified structure of SC based on QFG MOSFET is proposed in this section. Figure 1  Here in Figure 1(a), M1 operates in linear mode whereas M2 in saturation mode. As known the transconductance achieved is maxima when MOSFET operates in saturation so by changing M1 to saturation mode the effective transconductance of the SC structure can be enhanced which can be used in the design of high gain circuits. If Vth,M2<Vth,M1 is achieved then a possibility to increase VDS of M1 can be achieved. The necessary condition required to be satisfied for operating both the MOSFETs of SC in the saturation region is: To satisfy the condition of (1), QFG is used in the proposed SC design as shown in Figure 1 is the total capacitance seen at the QFG node of M2 and ' , GD MP C is the parasitic capacitance of MP. The capacitor C2 and MOSFET MP is used to realize M2 in QFG mode. As seen in (2), the effective threshold of M2 gets scaled down which increases the possibility of satisfying the condition of (1) and the MOSFET M1 enters into saturation. As both the MOSFETs of SC turns in saturation, the effective transconductance gets increased. The analysis of the proposed QFG-SC structure of Figure 1(b) is shown below with its small-signal model shown in Figure 2.  (3)  Similarly performing the analysis of conventional SC structure shown in Figure 1(a), Comparing (8) and (9), the advantage of using the QFG technique in self-cascode can be easily observed in terms of the significant increase in resistance, approximately equal to that of a cascode. The effective transconductance of the proposed QFG-SC is calculated as:

Proposed Current Mirror
Current mirror (CM) is a circuit that generates the output as a replica of input current at a high impedance node so as to avoid the constant current irrespective of the type of load. Current mirror with wide operating range, better bandwidth, low input, and high output resistances are some of the key requirements. The gate driven cascode current mirror which fulfills the current mirror requirements is shown in Figure 3(a). The input MOSFETs M1 and M3 are configured as diode connected. The input current and output current is shown by iin and iout respectively. The output resistance is boosted by the intrinsic gain of cascode MOSFET M1, i.e. by gmr0. However, such CM suffers from poor voltage swing. Yet another configuration, self cascode provides the same feature with better swing. The schematic of the current mirror design based on conventional SC and based on proposed QFG-SC is shown in Figure 3(b) and Figure 3(c) respectively. In Figure 3 From the analysis of the standard current mirror, it has been observed that the input resistance is inversely proportional whereas the output resistance is directly proportional to the transconductance of MOSFETs used for current mirroring purpose. So, in Figure 3(b), by changing the mode of operation of M3 from linear to saturation enhances the transconductance of the SC which helps in reducing the input resistance and also the similar effect on M4 enhances the output resistance. These conditions were achieved by using QFG MOSFET M1 and M2 as shown in Figure 3(c).

Small signal analysis
The small signal analysis in terms of input resistance, output resistance, and bandwidth of current mirror based on proposed QFG-SC is carried out and also compared with that of based on conventional SC structure and standard cascode structure. The symbols used throughout the analysis are the standard spice model parameters of MOSFET and have their usual meaning.

Input resistance
The small signal model for calculating the input resistance (Rin,QFG-SC) of the proposed current mirror is shown in Figure 4.

Output resistance
The small signal model for calculating the output resistance (Rout,QFG-SC) of the proposed current mirror is shown in Figure 5.
Comparing (25), (26), and (27), it can be observed that for the proposed QFG SC based current mirror the output resistance is almost equal to that of cascode but compared to the conventional SC structure, it is boosted approximately by (gm2r04) factor.

Bandwidth
The small signal model for calculating bandwidth is shown in Figure 6. The output conductance and the gd C effects are neglected in comparison to gs C of the saturation mode transistors.
At node 2, From (28)    From (25) and (37), a slight variation in the bandwidth can be observed. However, the same remains for that of cascode.

Simulation Results
The device dimensions taken for simulation purposes for current mirror designs of Figure 3 are shown in Table 1. The channel length of the transistors is kept at its minimum value. The other assumed parameters for circuit simulations are also listed. The simulation results well support the mathematical analysis of the proposed design. The current transfer characteristic curve and their current copying accuracy error percentage for the input current ranging from 0 to 500uA are shown in Figure 7 and Figure 8 respectively.  The minimum error is found for the proposed QFG-SC current mirror circuit when compared to its conventional design. The input characteristic over input current ranging from 0 to 500uA is shown in Figure 9 where the disadvantage of using cascode when it comes to voltage headroom can be seen. The input and output resistance plots are shown in Figure 10 and Figure 11 respectively. Compared to conventional SC based CM, the proposed QFG-SC based CM input resistance becomes independent of (1/gm1) which results in reduced resistance to 940  from 1.6K . The lowest input resistance is exhibited by the proposed QFG-SC CM. Similarly, comparing the output resistance in relation to the conventional cascode it gets increased by (gm2r04) times due to which the resistance is increased to 170K  from 50K  . However, the output resistance is approximately equal to that of cascode. The frequency response is shown in Figure 12 where no bandwidth degradation is observed. The complete simulated Spice result is shown in tabulated form in Table 2.

Conclusion
In this paper, a high performance design of self cascode structure has been presented. The improvement achieved is in terms of transconductance that has been possible due to change in the transistor mode of operation, possible by using the QFG technique. Further, the proposed QFG-SC structure is used in current mirror realizations which improved the parameters in terms of input and output resistances without affecting the bandwidth response. The performances achieved encourages its application in low power design.