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The development of integrated circuits becomes more complex and gets more susceptible to manufacturing errors as technology nodes get smaller. Along with that, the observability of more complex chips gets reduced, making it harder and more expensive to test. Therefore, the impact of different faults must be observed on the design as early as possible, in order to reduce the time to market and the cost of the fault to the project.
Since many designs depend on Digital Signal Processing applications, this project proposes a case study of the implementation of a FIR filter design in Verilog and the analysis and comparison of its response by inserting stuck-at faults in its shift registers via test bench simulation.
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